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ngc 1.5.0
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ngc 1.5.0
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#include <ngc/core/ngcdrv.h>Go to the source code of this file.
| #define _ngcbSEQ_ADDR_SHRAM 0x00003110 |
shfit RAM base register
| #define _ngcbSEQ_ADDR_SHSIZE 0x00003102 |
shfit size register
| #define _ngcbSEQ_ADDR_SHSTART 0x00003101 |
shfit start register
| #define _ngcbSEQ_ADDR_SLXCMD 0x00003100 |
selex command register
| #define _ngcbSEQ_ADDR_SLXSTAT 0x00003100 |
selex status register
| #define ngcbADC_ADDR_CTRL 0x00003000 |
ADC control register
| #define ngcbADC_ADDR_DELAY 0x00003001 |
conversion strobe delay
| #define ngcbADC_ADDR_FCNT 0x00003011 |
Fowler counter register
| #define ngcbADC_ADDR_FMODE 0x00003013 |
Fowler mode register
| #define ngcbADC_ADDR_FSIZE 0x00003010 |
Fowler size register
| #define ngcbADC_ADDR_MON 0x0000B000 |
video signal monitor
| #define ngcbADC_ADDR_RST 0x00003003 |
reset data chain
| #define ngcbADC_ADDR_STAT 0x00003000 |
ADC status register
| #define ngcbADC_ADDR_SUBSAMP 0x00003012 |
sub-pixel sampling register
| #define ngcbADC_CHAINFIRST 0x01000000 |
first in chain bit
| #define ngcbADC_CLAMP 0x00000040 |
clamp and sample mode
| #define ngcbADC_CONVERT1 0x00100000 |
enable conversion signal 1
| #define ngcbADC_CONVERT2 0x00200000 |
enable conversion signal 2
| #define ngcbADC_DLINK 0x80000000 |
ADC dual-link mode
| #define ngcbADC_ENABLE 0x0000003F |
enable ADC components
| #define ngcbADC_FILTER 0x00000080 |
filter on-off
| #define ngcbADC_LED_OFF 0x02000000 |
LEDs off
| #define ngcbADC_MAX_DELAY 1024 |
max. conversion strobe delay
| #define ngcbADC_MAX_ENABLE ngcbADC_ENABLE |
max. enabled ADCs
| #define ngcbADC_MAX_PKTSIZE 0xFF |
max. packet size
| #define ngcbADC_MAX_RXCNT 0xF |
max. packet counter
| #define ngcbADC_MODE_NORMAL 0x0 |
normal mode
| #define ngcbADC_MODE_SIM 0x1 |
simulation
| #define ngcbADC_OP_MODE 0x10000000 |
ADC operation mode
| #define ngcbADC_PKTSIZE 0x0000FF00 |
packet size (in data-words)
| #define ngcbADC_RXCNT 0x000F0000 |
packet counter
| #define ngcbADC_SIM_CNT 0x1 |
simulate counter on channels
| #define ngcbADC_SIM_MODE 0x20000000 |
ADC simulation mode
| #define ngcbADC_SIM_NUMBERS 0x0 |
simulate channel numbers
| #define ngcbAFE_PORT 0xF000 |
AFE virtual i/o-port
| #define ngcbAL0_ADC1_CTRL 0x9700 |
ALICE ADC1 control - rev. 0
| #define ngcbAL0_ADC1_DATA 0x9701 |
ALICE ADC1 data - rev. 0
| #define ngcbAL0_ADC2_CTRL 0x9600 |
ALICE ADC2 control - rev. 0
| #define ngcbAL0_ADC2_DATA 0x9601 |
ALICE ADC2 data - rev. 0
| #define ngcbAL0_ADC3_CTRL 0x9500 |
ALICE ADC3 control - rev. 0
| #define ngcbAL0_ADC3_DATA 0x9501 |
ALICE ADC3 data - rev. 0
| #define ngcbAL0_ADC4_CTRL 0x9400 |
ALICE ADC4 control - rev. 0
| #define ngcbAL0_ADC4_DATA 0x9401 |
ALICE ADC4 data - rev. 0
| #define ngcbAL_ADC1_CTRL 0xA700 |
ALICE ADC1 control
| #define ngcbAL_ADC1_DATA 0xA701 |
ALICE ADC1 data
| #define ngcbAL_ADC2_CTRL 0xA600 |
ALICE ADC2 control
| #define ngcbAL_ADC2_DATA 0xA601 |
ALICE ADC2 data
| #define ngcbAL_ADC3_CTRL 0xA500 |
ALICE ADC3 control
| #define ngcbAL_ADC3_DATA 0xA501 |
ALICE ADC3 data
| #define ngcbAL_ADC4_CTRL 0xA400 |
ALICE ADC4 control
| #define ngcbAL_ADC4_DATA 0xA401 |
ALICE ADC4 data
| #define ngcbAL_ADC_LB 0x9800 |
ALICE telemetry ADC (left)
| #define ngcbAL_ADC_RB 0x9900 |
ALICE telemetry ADC (right)
| #define ngcbAL_DAC12_CTRL 0x9000 |
DAC 1 and 2 control
| #define ngcbAL_DAC1_DATA 0x9002 |
DAC 1 data
| #define ngcbAL_DAC2_DATA 0x9001 |
DAC 2 data
| #define ngcbAL_DAC34_CTRL 0x9100 |
DAC 3 and 4 control
| #define ngcbAL_DAC3_DATA 0x9102 |
DAC 3 data
| #define ngcbAL_DAC4_DATA 0x9101 |
DAC 4 data
| #define ngcbAL_PHASES 0xA200 |
ALICE phases - A20C
| #define ngcbAO_ADDR_AFE_L 0x8600 |
AO AFE left side
| #define ngcbAO_ADDR_AFE_R 0x8601 |
AO AFE right side
| #define ngcbAO_ADDR_CTRL 0x3004 |
AO-head control register
| #define ngcbAO_ADDR_DELAY1 0x8300 |
AO-head delay register1
| #define ngcbAO_ADDR_DELAY2 0x8301 |
AO-head delay register2
| #define ngcbAO_ADDR_DELAY3 0x8302 |
AO-head delay register3
| #define ngcbAO_ADDR_DELAY4 0x8303 |
AO-head delay register4
| #define ngcbAO_ADDR_DELAY5 0x8304 |
AO-head delay register5
| #define ngcbAO_ADDR_DIM 0x8500 |
AO image dimension register
| #define ngcbAO_ADDR_FCNT 0x8405 |
Current frame counter - RDONLY
| #define ngcbAO_ADDR_FRATE 0x8406 |
Actual frame rate (Hz) - RDONLY
| #define ngcbAO_ADDR_IPHLVL 0x8200 |
I-phase-level register
| #define ngcbAO_ADDR_PHCTRL 0x8202 |
Parallel-phases ctrl-register
| #define ngcbAO_ADDR_SENS1 0x8400 |
AO sensor-1 register (temp,hum)
| #define ngcbAO_ADDR_SENS2 0x8401 |
AO sensor-2 register (pressure)
| #define ngcbAO_ADDR_SENS3 0x8402 |
AO sensor-3 register (pressure)
| #define ngcbAO_ADDR_SENS4 0x8403 |
AO sensor-4 register (pressure)
| #define ngcbAO_ADDR_SENS5 0x8404 |
AO sensor-5 register (pressure)
| #define ngcbAO_ADDR_SPHLVL 0x8201 |
S-phase-level register
| #define ngcbCLDC_ADC_RANGE 10.0 |
| #define ngcbCLDC_ADDR_BIAS 0x00008000 |
DAC register
| #define ngcbCLDC_ADDR_CTRL 0x00008001 |
CLDC control register
| #define ngcbCLDC_ADDR_MON1 0x0000B001 |
analog clock monitor 1
| #define ngcbCLDC_ADDR_MON2 0x0000B002 |
analog clock monitor 2
| #define ngcbCLDC_ADDR_PA 0x00008002 |
PREAMP DAC register
| #define ngcbCLDC_ADDR_TELCHAN 0x0000A000 |
telemetry channel
| #define ngcbCLDC_ADDR_TELDATA 0x0000A000 |
telemetry data
| #define ngcbCLDC_DAC_DATA 0x00003FFF |
DAC channel value
| #define ngcbCLDC_DAC_GAIN1 1.259 |
output gain
| #define ngcbCLDC_DAC_GAIN2 1.076 |
offset gain
| #define ngcbCLDC_DAC_NUM 0x003F0000 |
DAC channel number
| #define ngcbCLDC_DAC_SLCT 0x00200000 |
select DAC 1 or 2
| #define ngcbCLDC_DIODEBIAS1 0x3e |
diode bias 1
| #define ngcbCLDC_DIODEBIAS2 0x3f |
diode bias 2
| #define ngcbCLDC_ENABLE 0x00000001 |
output enable
| #define ngcbCLDC_FEB_MAX_CLK 18 |
maximum number of FEB clocks
| #define ngcbCLDC_FEB_MAX_DC 20 |
maximum number of FEB biases
| #define ngcbCLDC_ILCK 0x00000004 |
interlock enable
| #define ngcbCLDC_MAX_CLK 24 |
maximum number of clocks
| #define ngcbCLDC_MAX_DC 128 |
maximum number of biases
| #define ngcbCLDC_OFF_SLCT 0x80000000 |
select DAC offset
| #define ngcbCLDC_PAOFF1 0x3c |
preamplifier offset 1
| #define ngcbCLDC_PAOFF2 0x3d |
preamplifier offset 2
| #define ngcbCLDC_PROT_OFF 0x00000010 |
protection disable
| #define ngcbCLDC_SET_ZERO 0x00008000 |
set all voltages to zero
| #define ngcbCLDC_STAT_DISABLED 0 |
output disabled
| #define ngcbCLDC_STAT_ENABLED 1 |
output enabled
| #define ngcbCLDC_TEL_CHAN 0x0000003F |
telemetry channel
| #define ngcbCLDC_TEL_DATA 0x0000FFFF |
telemetry data value
| #define ngcbCLDC_VIDOFF1 0x3a |
video offset 1
| #define ngcbCLDC_VIDOFF2 0x3b |
video offset 2
| #define ngcbDFE_ADDR_DATE 0x00001010 |
firmware date
| #define ngcbDFE_ADDR_ID 0x00001002 |
id and revision register
| #define ngcbDFE_ADDR_NULL 0x0 |
| #define ngcbDFE_ADDR_RTMS 0x00003200 |
RTMS configuration base
| #define ngcbDFE_ADDR_SERNO1 0x00001006 |
serial number bits 0-31
| #define ngcbDFE_ADDR_SERNO2 0x00001008 |
serial number bits 32 - 47
| #define ngcbDFE_ADDR_SERNO_SEL 0x0000100A |
component selection
| #define ngcbDFE_ADDR_STAT 0x00001000 |
status register
| #define ngcbDFE_ADDR_TEMP 0x0000100C |
temperature sensor
| #define ngcbDFE_ADDR_TSU 0x00003100 |
TSU trigger base
| #define ngcbDFE_ADDR_UPDATE 0x0000D000 |
firmware update register
| #define ngcbDFE_CFG_HDR_DOWN1 0x5 |
down-link 1
| #define ngcbDFE_CFG_HDR_DOWN2 0x6 |
down-link 2
| #define ngcbDFE_CFG_HDR_DOWN3 0x7 |
down-link 3
| #define ngcbDFE_CFG_HDR_MAX NGCDRV_CTRL_MAXHDR |
maximum header value
| #define ngcbDFE_CFG_HDR_SELF 0x2 |
select this module
| #define ngcbDFE_CFG_HDR_SYS NGCDRV_CTRL_SYSHDR |
system ctrl header
| #define ngcbDFE_CFG_RESET NGCDRV_CTRL_SYSRESET |
global system reset
| #define ngcbDFE_ID_FIRMWARE 0x000FF000 |
firmware revision
| #define ngcbDFE_ID_PRODUCT 0x000000FF |
product-code
| #define ngcbDFE_ID_REV 0x00000F00 |
hardware revision
| #define ngcbDFE_ID_SUBTYPE 0x000000F0 |
board version
| #define ngcbDFE_ID_TYPE 0x0000000F |
board type (FEB,AQ32,...)
| #define ngcbDFE_SERNO_BACK 0x3 |
backplane serial number
| #define ngcbDFE_SERNO_BOARD 0x1 |
board serial number
| #define ngcbDFE_SERNO_TRANS 0x2 |
transition board serial number
| #define ngcbDFE_STAT_BIAS_HI 0x00001000 |
flag bias high
| #define ngcbDFE_STAT_BIAS_LO 0x00002000 |
flag bias low
| #define ngcbDFE_STAT_CHAN1 0x00000004 |
downstream 1 up
| #define ngcbDFE_STAT_CHAN2 0x00010000 |
downstream 2 up
| #define ngcbDFE_STAT_CHAN3 0x00020000 |
downstream 3 up
| #define ngcbDFE_STAT_CLDC 0x40000000 |
CLDC status (enabled)
| #define ngcbDFE_STAT_CLK_HI 0x00004000 |
flag clock high
| #define ngcbDFE_STAT_CLK_LO 0x00008000 |
flag clock low
| #define ngcbDFE_STAT_FRAMERR0 0x00000800 |
down-link framing error
| #define ngcbDFE_STAT_FRAMERR1 0x00000200 |
up-link 1 framing error
| #define ngcbDFE_STAT_FRAMERR2 0x00000400 |
up-link 2 framing error
| #define ngcbDFE_STAT_HARDERR0 0x00000020 |
down-link hard error
| #define ngcbDFE_STAT_HARDERR1 0x00000008 |
up-link 1 hard error
| #define ngcbDFE_STAT_HARDERR2 0x00000010 |
up-link 2 hard error
| #define ngcbDFE_STAT_ILCK 0x00080000 |
external interlock
| #define ngcbDFE_STAT_NEXT_EMPTY 0x20000000 |
next link FIFO empty
| #define ngcbDFE_STAT_NEXT_FULL 0x10000000 |
next link FIFO full
| #define ngcbDFE_STAT_OVRILLUM 0x00040000 |
AO over-illumination flag
| #define ngcbDFE_STAT_RXC_EMPTY 0x00200000 |
RX COM FIFO empty
| #define ngcbDFE_STAT_RXC_FULL 0x00100000 |
RX COM FIFO full
| #define ngcbDFE_STAT_SEQ 0x80000000 |
SEQ status (running)
| #define ngcbDFE_STAT_SIDE 0x00000002 |
sidestream up
| #define ngcbDFE_STAT_SOFTERR0 0x00000100 |
down-link soft error
| #define ngcbDFE_STAT_SOFTERR1 0x00000040 |
up-link 1 soft error
| #define ngcbDFE_STAT_SOFTERR2 0x00000080 |
up-link 2 soft error
| #define ngcbDFE_STAT_TXA1_EMPTY 0x00400000 |
TX ACQ1 FIFO empty
| #define ngcbDFE_STAT_TXA1_FULL 0x01000000 |
TX ACQ1 FIFO full
| #define ngcbDFE_STAT_TXA2_EMPTY 0x00800000 |
TX ACQ2 FIFO empty
| #define ngcbDFE_STAT_TXA2_FULL 0x02000000 |
TX ACQ2 FIFO full
| #define ngcbDFE_STAT_TXC_EMPTY 0x08000000 |
TX COM FIFO empty
| #define ngcbDFE_STAT_TXC_FULL 0x04000000 |
TX COM FIFO full
| #define ngcbDFE_STAT_UPLINK 0x00000001 |
upstream link up
| #define ngcbDFE_TYPE_AOWFS 4 |
AO-head (wave front sensor)
| #define ngcbDFE_TYPE_APCIe 0xB |
Adaptive PCIexpress interface
| #define ngcbDFE_TYPE_AQ32 2 |
32 channel ADC board
| #define ngcbDFE_TYPE_AQ32_10MHZ 5 |
32 channel 10 MHz ADC board
| #define ngcbDFE_TYPE_FEB 1 |
front-end basic board
| #define ngcbDFE_TYPE_HIGHSPEED 3 |
high-speed FEB
| #define ngcbDFE_TYPE_NGSD 6 |
NGSD camera
| #define ngcbDFE_TYPE_NODE 0xF |
node
| #define ngcbDFE_TYPE_PCI 8 |
PCI-bus interface
| #define ngcbDFE_TYPE_PCIe 0xA |
PCIexpress interface
| #define ngcbDFE_TYPE_PMC 9 |
PMC interface (LCU, real-time)
| #define ngcbDFE_TYPE_UNKNOWN 0 |
unknown board type
| #define ngcbDFE_TYPE_WFS 7 |
WFS cameras (ALICE, LISA, ...)
| #define ngcbHDR_GEN_IO 0xC |
general purpose I/O
| #define ngcbHDR_IFC 0xF |
access interface base class
| #define ngcbHDR_PCI_CFG 0xA |
PCI configuration space
| #define ngcbHDR_PCI_LOCAL 0xB |
PCI local space
| #define ngcbHDR_RESET 0xD |
interface device reset
| #define ngcbI2C_CLK_LINE 0 |
clock-line bit
| #define ngcbI2C_DATA_LINE 1 |
data-line bit
| #define ngcbI2C_PCF8575 0x4 |
PCF8575 fixed address
| #define ngcbI2C_PORT 0x0000C000 |
I2C-port register address
| #define ngcbIFC_ADDR_DATE 0xB4 |
firmware date
| #define ngcbIFC_ADDR_ID 0xA0 |
id-register
| #define ngcbIFC_ADDR_SCNT 0xD4 |
sync counter status
| #define ngcbIFC_ADDR_SCTL 0xD8 |
sync control
| #define ngcbIFC_ADDR_SERNO1 0xB8 |
serial number low
| #define ngcbIFC_ADDR_SERNO2 0xBC |
serial number high
| #define ngcbIFC_ADDR_SETUP 0xC8 |
setup register
| #define ngcbIFC_ADDR_STATUS 0x14 |
status
| #define ngcbIFC_ADDR_TEMP 0xA4 |
temperature
| #define ngcbIFC_CMD_FAILED 0x20000000 |
command failed
| #define ngcbIFC_FIFO_SIZE NGCDRV_COM_FIFO_SIZE |
COM FIFO size
| #define ngcbIFC_NOT_OPEN 0x10000000 |
device not open
| #define ngcbIFC_SIM 0x40000000 |
simulation mode
| #define ngcbIFC_STAT_ACK NGCDRV_STAT_ACK |
acknowledge
| #define ngcbIFC_STAT_FRAM_ERR NGCDRV_STAT_FRAM_ERR |
link framing error
| #define ngcbIFC_STAT_HARD_ERR NGCDRV_STAT_HARD_ERR |
link hard error
| #define ngcbIFC_STAT_LINK_UP NGCDRV_STAT_LINK_UP |
link up
| #define ngcbIFC_STAT_RX_EMPTY NGCDRV_STAT_RX_EMPTY |
RX FIFO empty
| #define ngcbIFC_STAT_RX_FULL NGCDRV_STAT_RX_FULL |
RX FIFO full
| #define ngcbIFC_STAT_SOFT_ERR NGCDRV_STAT_SOFT_ERR |
link soft error
| #define ngcbIFC_STAT_TX_EMPTY NGCDRV_STAT_TX_EMPTY |
TX FIFO empty
| #define ngcbIFC_STAT_TX_FULL NGCDRV_STAT_TX_FULL |
TX FIFO FULL
| #define ngcbIFC_STAT_VALID NGCDRV_STAT_VALID |
address valid
| #define ngcbLISA_ADC_BOT 0x9900 |
LISA telemetry ADC (bottom)
| #define ngcbLISA_ADC_TOP 0x9800 |
LISA telemetry ADC (top)
| #define ngcbLISA_ADDR_CHAN 0x9B00 |
LISA rev 0 channel enable/disable
| #define ngcbLISA_ADDR_GAIN 0xA100 |
LISA gain base map
| #define ngcbLISA_ADDR_GAIN_BOT 0x9C20 |
LISA rev 0 gain map (bottom)
| #define ngcbLISA_ADDR_GAIN_TOP 0x9C00 |
LISA rev 0 gain map (top)
| #define ngcbLISA_ADDR_RG 0xA001 |
LISA row-group addres
| #define ngcbMAX_MOD 16 |
Maximum number of nested modules
| #define ngcbNUM_LINK 3 |
Number of downlinks for network
| #define ngcbPREAMP_ADDR_CTRL 0x0000C400 |
preamplifier control register
| #define ngcbRES_ERR_ADDR 0x00000004 |
Wrong address
| #define ngcbRES_ERR_DATA 0x00000005 |
Wrong data
| #define ngcbRES_ERR_HDR 0x00000003 |
Wrong header
| #define ngcbRES_ERR_I2C 0x00000010 |
I2C-bus error
| #define ngcbRES_ERR_INTR 0x00000200 |
I/O interrupted
| #define ngcbRES_ERR_IO 0x00000100 |
I/O error
| #define ngcbRES_ERR_LINK_DOWN 0x00002000 |
Link channel down
| #define ngcbRES_ERR_LINK_FRAM 0x00010000 |
Link channel framing error
| #define ngcbRES_ERR_LINK_HARD 0x00004000 |
Link channel hard error
| #define ngcbRES_ERR_LINK_SOFT 0x00008000 |
Link channel soft error
| #define ngcbRES_ERR_NOT_OPEN 0x00000007 |
Device not open
| #define ngcbRES_ERR_OPEN 0x00000400 |
Error opening device
| #define ngcbRES_ERR_RESET 0x00000800 |
Error resetting device
| #define ngcbRES_ERR_TIMEOUT 0x00001000 |
Timeout
| #define ngcbRES_ERR_XSIZE 0x00000006 |
Wrong transfer size
| #define ngcbRES_OP_FAILURE 0x00000002 |
Operation failed
| #define ngcbRES_OP_INVALID 0x00000001 |
Invalid address or function
| #define ngcbRES_SUCCESS 0x00000000 |
Successful operation
| #define ngcbRPC_AMC 0 |
AMC
| #define ngcbRPC_BUILD_INFO 0x00000005 |
Get build info
| #define ngcbRPC_CHAN_COUNT 0x00020002 |
Get number of monitor-channels
| #define ngcbRPC_CMDS 0x00000006 |
Get command classes
| #define ngcbRPC_DAC_SNAPSHOT 0x00060004 |
Get DAC snapshot
| #define ngcbRPC_DEBUG_LOG 0x00000004 |
Get debug log
| #define ngcbRPC_FW_VERSION 0x00000003 |
Get firmware version
| #define ngcbRPC_GET_APD_ENA 0x10030002 |
Get APD output enable
| #define ngcbRPC_GET_APD_ILCK 0x10030003 |
Get APD interlock state
| #define ngcbRPC_GET_BANK_BYPASS 0x10040004 |
Get BANK bypass
| #define ngcbRPC_GET_BANK_CNCL 0x10020004 |
Get BANK BIAS cancel
| #define ngcbRPC_GET_BANK_CROSS 0x10040002 |
Get BANK cross mode
| #define ngcbRPC_GET_BANK_ENA 0x10020002 |
Get BANK enable
| #define ngcbRPC_GET_BANK_FILT 0x1002000A |
Get BANK filter
| #define ngcbRPC_GET_BANK_GAIN 0x10020008 |
Get BANK gain
| #define ngcbRPC_GET_BANK_SHORT 0x10020006 |
Get BANK short
| #define ngcbRPC_GET_CHAN_BITS 0x20F00002 |
Get sample bit width
| #define ngcbRPC_GET_CHAN_DROP 0x20100003 |
Get channel drop flags
| #define ngcbRPC_GET_CHAN_ENA 0x000E0004 |
Get RTMS channel enable
| #define ngcbRPC_GET_CHAN_FRM 0x000E000C |
Get RTMS channel FRAME config
| #define ngcbRPC_GET_CHAN_IP 0x000E0006 |
Get RTMS channel IP config
| #define ngcbRPC_GET_CHAN_MAP 0x20200002 |
Set sample map (select & sort)
| #define ngcbRPC_GET_CHAN_MUDPI 0x000E0008 |
Get RTMS channel MUDPI config
| #define ngcbRPC_GET_CHAN_RTMS 0x000E000A |
Get RTMS channel RTMS config
| #define ngcbRPC_GET_CHAN_SHIFT 0x20F00004 |
Get sample bit shift
| #define ngcbRPC_GET_CHAN_SRC 0x20100002 |
Get channel sources
| #define ngcbRPC_GET_DACCHAN 0x00060003 |
Get DAC channel value
| #define ngcbRPC_GET_DACLIST 0x00060001 |
Get DAC channel list
| #define ngcbRPC_GET_FBANK_ENA 0x10010008 |
Get fast bank anable
| #define ngcbRPC_GET_FBANK_LIM 0x1001000A |
Get fast bank slew rate limit
| #define ngcbRPC_GET_FP_PORTCFG 0x00050003 |
Get front panel port config
| #define ngcbRPC_GET_FP_PORTS 0x00050001 |
Get front panel ports
| #define ngcbRPC_GET_FP_SIG 0x00050002 |
Get front panel signals
| #define ngcbRPC_GET_INIT_PAT 0x000F0004 |
Set sequencer init pattern
| #define ngcbRPC_GET_PBANK_ENA 0x10010002 |
Get slow phys. bank enable
| #define ngcbRPC_GET_PBANK_SRC 0x10010004 |
Get slow phys. bank source
| #define ngcbRPC_GET_PSU_ENA 0x1002000C |
Get PSU enable
| #define ngcbRPC_GET_RTMS_NET 0x000E0002 |
Get RTMS common parameters
| #define ngcbRPC_GET_SCLK_LIM 0x10010006 |
Get slow clock slew rate limit
| #define ngcbRPC_I2C 0x10040013 |
AQ8 raw I2C
| #define ngcbRPC_ID 0x00000002 |
Get controller ID
| #define ngcbRPC_MON_INFO 0x00020003 |
Get monitoring channel data
| #define ngcbRPC_MON_THR 0x00020004 |
Set monitoring thresholds
| #define ngcbRPC_NOP 0x00000001 |
NOP
| #define ngcbRPC_OUTPUT_OFF 0x00090003 |
Disable output
| #define ngcbRPC_OUTPUT_ON 0x00090002 |
Enable output
| #define ngcbRPC_OUTPUT_STATUS 0x00090001 |
Get output status
| #define ngcbRPC_PRG_FLASH 0x00010001 |
Program flash
| #define ngcbRPC_RST_APD_ILCK 0x10030004 |
Reset APD interlock
| #define ngcbRPC_RST_ARP 0x000E0010 |
Reset ARP table
| #define ngcbRPC_RTM 1 |
RTM
| #define ngcbRPC_SET_APD_ENA 0x10030001 |
Set APD output enable
| #define ngcbRPC_SET_BANK_BYPASS 0x10040003 |
Set BANK bypass
| #define ngcbRPC_SET_BANK_CNCL 0x10020003 |
Set BANK BIAS cancel
| #define ngcbRPC_SET_BANK_CROSS 0x10040001 |
Set BANK cross mode
| #define ngcbRPC_SET_BANK_ENA 0x10020001 |
Set BANK enable
| #define ngcbRPC_SET_BANK_FILT 0x10020009 |
Set BANK filter
| #define ngcbRPC_SET_BANK_GAIN 0x10020007 |
Set BANK gain
| #define ngcbRPC_SET_BANK_SHORT 0x10020005 |
Set BANK short
| #define ngcbRPC_SET_CHAN_BITS 0x20F00001 |
Set sample bit width
| #define ngcbRPC_SET_CHAN_ENA 0x000E0003 |
Set RTMS channel enable
| #define ngcbRPC_SET_CHAN_FRM 0x000E000B |
Set RTMS channel FRAME config
| #define ngcbRPC_SET_CHAN_IP 0x000E0005 |
Set RTMS channel IP config
| #define ngcbRPC_SET_CHAN_MAP 0x20200001 |
Set sample map (select & sort)
| #define ngcbRPC_SET_CHAN_MUDPI 0x000E0007 |
Set RTMS channel MUDPI config
| #define ngcbRPC_SET_CHAN_RTMS 0x000E0009 |
Set RTMS channel RTMS config
| #define ngcbRPC_SET_CHAN_SHIFT 0x20F00003 |
Set sample bit shift
| #define ngcbRPC_SET_CHAN_SRC 0x20100001 |
Set channel sources
| #define ngcbRPC_SET_DACCHAN 0x00060002 |
Set DAC channel value
| #define ngcbRPC_SET_FBANK_ENA 0x10010007 |
Set fast bank enable
| #define ngcbRPC_SET_FBANK_LIM 0x10010009 |
Set fast bank slew rate limit
| #define ngcbRPC_SET_FP_PORTCFG 0x00050004 |
Set front panel port config
| #define ngcbRPC_SET_INIT_PAT 0x000F0003 |
Set sequencer init pattern
| #define ngcbRPC_SET_PBANK_ENA 0x10010001 |
Set slow phys. bank enable
| #define ngcbRPC_SET_PBANK_SRC 0x10010003 |
Set slow phys. bank source
| #define ngcbRPC_SET_PSU_ENA 0x1002000B |
Set PSU enable
| #define ngcbRPC_SET_RTMS_NET 0x000E0001 |
Set RTMS common parameters
| #define ngcbRPC_SET_SCLK_LIM 0x10010005 |
Set slow clock slew rate limit
| #define ngcbRPC_SNAPSHOT 0x00020001 |
Get monitoring snapshot
| #define ngcbRPC_TSU_GET 0x000D0001 |
Get TSU timestamp
| #define ngcbRPC_TSU_GET_CFG 0x000D0007 |
Get last TSU configuration
| #define ngcbRPC_TSU_START 0x000D0004 |
Start TSU
| #define ngcbRPC_TSU_START_N 0x000D0006 |
Start TSU for N cycles
| #define ngcbRPC_TSU_STATUS 0x000D0002 |
Get TSU status
| #define ngcbRPC_TSU_STOP 0x000D0005 |
Stop TSU
| #define ngcbRPC_TSU_TRIGGER 0x000D0003 |
TSU manual trigger
| #define ngcbSCAIO_ADDR_CFGFIFO 0x00002000 |
ASIC configuration FIFO
| #define ngcbSCAIO_ADDR_CMD 0x00002700 |
ASIC command register
| #define ngcbSCAIO_ADDR_DCMD 0x00003700 |
ASIC data command register
| #define ngcbSCAIO_ADDR_DELAY 0x00002702 |
ASIC delay register
| #define ngcbSCAIO_ADDR_RESPFIFO 0x00002400 |
ASIC response FIFO
| #define ngcbSCAIO_ADDR_STATUS 0x00002701 |
ASIC status register
| #define ngcbSCAIO_CMD_INIT 0x80000000 |
ASIC initialize
| #define ngcbSCAIO_CMD_RD 0x00001000 |
ASIC read-operation
| #define ngcbSCAIO_CMD_RESET 0x40000000 |
ASIC reset subsystem
| #define ngcbSCAIO_CMD_START 0x00008000 |
ASIC start transfer
| #define ngcbSCAIO_CMD_START_RD (ngcbSCAIO_CMD_START | ngcbSCAIO_CMD_RD) |
ASIC start read
| #define ngcbSCAIO_CMD_START_WR ngcbSCAIO_CMD_START |
ASIC start write
| #define ngcbSCAIO_CMD_TEST 0x00010000 |
ASIC test mode
| #define ngcbSCAIO_DCMD_INIT 0x80000000 |
initialize ASIC data interface
| #define ngcbSCAIO_DCMD_START 0x00001000 |
start ASIC data interface
| #define ngcbSCAIO_FIFO_SIZE 515 |
ASIC FIFO size
| #define ngcbSCAIO_PORT 0xa0000000 |
ASIC address specifier
| #define ngcbSCAIO_STAT_CFGFIFO_EMPTY 0x00000001 |
cfg.-FIFO empty
| #define ngcbSCAIO_STAT_RD_IDLE 0x00000020 |
read idle
| #define ngcbSCAIO_STAT_RDWAITSTART 0x00000040 |
read wait for start
| #define ngcbSCAIO_STAT_RESPFIFO_EMPTY 0x00000010 |
resp FIFO empty
| #define ngcbSCAIO_STAT_RESPFIFO_FULL 0x00000080 |
resp.-FIFO full
| #define ngcbSCAIO_STAT_WR_IDLE 0x00000002 |
write idle
| #define ngcbSEQ_ADDR_CTRL 0x00006000 |
SEQ control register
| #define ngcbSEQ_ADDR_INITHIGH 0x00006003 |
pattern init high
| #define ngcbSEQ_ADDR_INITLOW 0x00006002 |
pattern init low
| #define ngcbSEQ_ADDR_MODE 0x0000E006 |
SEQ mode register
| #define ngcbSEQ_ADDR_MON 0x0000B003 |
digital clock monitor
| #define ngcbSEQ_ADDR_PATRAM_HIGH 0x00005000 |
pattern RAM bits 32-64
| #define ngcbSEQ_ADDR_PATRAM_LOW 0x00004800 |
pattern RAM bits 0-31
| #define ngcbSEQ_ADDR_SEQRAM 0x00004000 |
sequencer program RAM
| #define ngcbSEQ_ADDR_STAT 0x00006000 |
SEQ status register
| #define ngcbSEQ_CLK_BREAK 0x20000000 |
break-point bit
| #define ngcbSEQ_CLK_CLAMP 0x00000004 |
clamp-sample
| #define ngcbSEQ_CLK_CONVERT1 0x00000001 |
convert 1
| #define ngcbSEQ_CLK_CONVERT2 0x00000002 |
convert 2
| #define ngcbSEQ_CLK_DISABLE1 0x00000080 |
disable bits 0..7
| #define ngcbSEQ_CLK_DISABLE2 0x00000100 |
disable bits 8..15
| #define ngcbSEQ_CLK_DISABLE3 0x00000200 |
disable bits 16..23
| #define ngcbSEQ_CLK_DISABLE4 0x00000400 |
disable bits 24..31
| #define ngcbSEQ_CLK_DISABLE5 0x00000800 |
TBD
| #define ngcbSEQ_CLK_DWELL 0x0FFFF000 |
pattern dwell time
| #define ngcbSEQ_CLK_LEMO1 0x00000008 |
signal on LEMO 1
| #define ngcbSEQ_CLK_LEMO2 0x00000010 |
signal on LEMO 2
| #define ngcbSEQ_CLK_LOW 0xFFFFFFFF |
clocks 1-32
| #define ngcbSEQ_CLK_PATEND 0x80000000 |
end of pattern bit
| #define ngcbSEQ_CLK_PRGEND 0x40000000 |
end of program bit
| #define ngcbSEQ_CLK_SYNC 0x10000000 |
wait for trigger bit
| #define ngcbSEQ_CLK_UTIL1 0x00000020 |
utility signal 1
| #define ngcbSEQ_CLK_UTIL2 0x00000040 |
utility signal 2
| #define ngcbSEQ_CODE_EXEC 0x1 |
execute pattern address n times
| #define ngcbSEQ_CODE_EXIT 0x7 |
exit program
| #define ngcbSEQ_CODE_JSR 0x5 |
jump to sub-routine address
| #define ngcbSEQ_CODE_LOOP 0x2 |
loop n times
| #define ngcbSEQ_CODE_LOOP_END 0x3 |
loop end
| #define ngcbSEQ_CODE_LOOP_INF 0x4 |
infinite loop
| #define ngcbSEQ_CODE_NOP 0x0 |
no operation
| #define ngcbSEQ_CODE_RETURN 0x6 |
return from sub-routine
| #define ngcbSEQ_CTRL_BREAK 0x00000008 |
stop at next break-point
| #define ngcbSEQ_CTRL_BREAKMODE 0x00000010 |
break-mode (NGCII)
| #define ngcbSEQ_CTRL_CVT_INT 0x00000004 |
disable external convert
| #define ngcbSEQ_CTRL_DISABLE 0x00000002 |
disable sync-run
| #define ngcbSEQ_CTRL_PAUSE 0x00000010 |
pause program execution
| #define ngcbSEQ_CTRL_RUNSYNC 0x00000001 |
synchronous run-signal
| #define ngcbSEQ_CTRL_STOP 0x00008000 |
stop and reset
| #define ngcbSEQ_CTRL_SYNC_OFF 0x00000020 |
disable sync pulse
| #define ngcbSEQ_CTRL_TRIGGER 0x00000080 |
software trigger signal
| #define ngcbSEQ_CTRL_TRIGGER_ON 0x00000040 |
enable trigger mode
| #define ngcbSEQ_CUR_ADDRESS 0x07FF0000 |
current pattern address
| #define ngcbSEQ_MAX_DWELLTIME (ngcbSEQ_CLK_DWELL >> 12) |
Maximum dwell time for one sequencer clock pattern state
| #define ngcbSEQ_MAX_OPEN_LOOPS 128 |
Maximum number of open loops (nesting depth)
| #define ngcbSEQ_MAX_REP (ngcbSEQ_RAM_CNT >> 11) |
Maximum pattern repetition factor
| #define ngcbSEQ_MAX_SUBRT 64 |
Maximum number of subroutines
| #define ngcbSEQ_MODE_SHUTTER 0x00000200 |
shutter mode
| #define ngcbSEQ_MON1 0x0000003F |
clock channel on LEMO-1
| #define ngcbSEQ_MON2 0x00003F00 |
clock channel on LEMO-2
| #define ngcbSEQ_MON3 0x003F0000 |
clock channel on LEMO-3
| #define ngcbSEQ_NUM_CLK 64 |
Number of sequencer clocks
| #define ngcbSEQ_PAT_BREAK (ngcbSEQ_PAT_IDLE | ngcbSEQ_CLK_BREAK) |
Sequencer BREAK-POINT pattern
| #define ngcbSEQ_PAT_IDLE |
Sequencer IDLE pattern
| #define ngcbSEQ_PAT_PRGEND (ngcbSEQ_PAT_IDLE | ngcbSEQ_CLK_PRGEND) |
Sequencer PROGRAM-END pattern
| #define ngcbSEQ_PAT_SYNC (ngcbSEQ_PAT_IDLE | ngcbSEQ_CLK_SYNC) |
Sequencer SYNC pattern
| #define ngcbSEQ_PATRAM_SIZE 2048 |
Sequencer pattern-RAM size (in words)
| #define ngcbSEQ_RAM_ADDR 0x000007FF |
address (optional)
| #define ngcbSEQ_RAM_CNT 0x07FFF800 |
counter (optional)
| #define ngcbSEQ_RAM_CODE 0x70000000 |
code
| #define ngcbSEQ_RAM_SIZE 2048 |
Sequencer RAM size (in words)
| #define ngcbSEQ_SHRAM_SIZE 9 |
shift RAM size in words
| #define ngcbSEQ_STAT_BREAK 0x00000020 |
break-point reached
| #define ngcbSEQ_STAT_EMPTY 0x00000040 |
pattern FIFO empty
| #define ngcbSEQ_STAT_EMPTY_READ 0x00000080 |
FIFO did become empty
| #define ngcbSEQ_STAT_FULL 0x00000100 |
pattern FIFO full
| #define ngcbSEQ_STAT_INTERP 0x00000001 |
code-interpreter running
| #define ngcbSEQ_STAT_PRGEND 0x00000010 |
programmed end reached
| #define ngcbSEQ_STAT_RUNNING 0x00000002 |
running
| #define ngcbSEQ_STAT_WAITING 0x00000004 |
waiting for trigger
| #define ngcbSEQ_TOK | ( | c, | |
| n, | |||
| r ) |
Create sequencer program token
| #define ngcbSHUTTER_ADDR_CTRL 0x0000E000 |
shutter control register
| #define ngcbSHUTTER_ADDR_EVT1 0x0000E002 |
shutter event counter 1
| #define ngcbSHUTTER_ADDR_EVT2 0x0000E003 |
shutter event counter 2
| #define ngcbSHUTTER_ADDR_EVT3 0x0000E004 |
shutter event counter 3
| #define ngcbSHUTTER_ADDR_EVT4 0x0000E005 |
shutter event counter 4
| #define ngcbSHUTTER_ADDR_EXP 0x0000E001 |
shutter exposure time
| #define ngcbSHUTTER_ADDR_STAT 0x0000E000 |
shutter status register
| #define ngcbSHUTTER_CLOCK 100000 |
Shutter clock in Hz (for counters)
| #define ngcbSHUTTER_CTRL_ABORT 0x00004000 |
abort
| #define ngcbSHUTTER_CTRL_AUX_OFF 0x00000004 |
disable AUX output
| #define ngcbSHUTTER_CTRL_DARK 0x00000800 |
dark exposure
| #define ngcbSHUTTER_CTRL_EVT1_RE 0x00000010 |
event 1 rising edge
| #define ngcbSHUTTER_CTRL_EVT2_RE 0x00000020 |
event 2 rising edge
| #define ngcbSHUTTER_CTRL_EVT3_RE 0x00000040 |
event 3 rising edge
| #define ngcbSHUTTER_CTRL_EVT4_RE 0x00000080 |
event 4 rising edge
| #define ngcbSHUTTER_CTRL_MODE 0x00000003 |
shutter mode
| #define ngcbSHUTTER_CTRL_OPEN_HI 0x00000400 |
open signal active high
| #define ngcbSHUTTER_CTRL_PAUSE 0x00002000 |
pause
| #define ngcbSHUTTER_CTRL_RESET 0x00001000 |
reset shutter module
| #define ngcbSHUTTER_CTRL_START 0x00008000 |
start
| #define ngcbSHUTTER_EVT_MASK 0xFFFFFFFF |
event mask
| #define ngcbSHUTTER_EXP_MASK 0xFFFFFFFF |
exposure time mask
| #define ngcbSHUTTER_STAT_COMPL 0x00001000 |
end of exposure
| #define ngcbSHUTTER_STAT_DARK 0x00000800 |
dark exposure
| #define ngcbSHUTTER_STAT_EVT1 0x00000001 |
event 1 encountered
| #define ngcbSHUTTER_STAT_EVT1_OVR 0x00000010 |
event 1 counter overrun
| #define ngcbSHUTTER_STAT_EVT2 0x00000002 |
event 2 encountered
| #define ngcbSHUTTER_STAT_EVT2_OVR 0x00000020 |
event 2 counter overrun
| #define ngcbSHUTTER_STAT_EVT3 0x00000004 |
event 3 encountered
| #define ngcbSHUTTER_STAT_EVT3_OVR 0x00000040 |
event 3 counter overrun
| #define ngcbSHUTTER_STAT_EVT4 0x00000008 |
event 4 encountered
| #define ngcbSHUTTER_STAT_EVT4_OVR 0x00000080 |
event 4 counter overrun
| #define ngcbSHUTTER_STAT_FAIL 0x00000100 |
failure
| #define ngcbSHUTTER_STAT_OPEN_HI 0x00000400 |
open signal active high
| #define ngcbSIM_SEQ_TIME 0x400 |
| #define ngcbSMALLBLOCK_IO 0x80000000 |
small block i/o flag
| #define ngcbSMALLBLOCK_RD_SIZE 8 |
maximum read-block size
| #define ngcbSMALLBLOCK_WR_SIZE 8 |
maximum write-block size
| #define ngcbSVS_ADDR 0x84E8 |
Supply voltage supervisor
| #define ngcbSVS_ADDR_SENS1 0x8488 |
sensor register (temp,hum)
| #define ngcbSVS_ADDR_SENS2 0x84C0 |
sensor register (pressure,temp)
| #define ngcbTESTERR_IO_ERR1 0x101 |
test message-send error
| #define ngcbTESTERR_IO_ERR2 0x102 |
test no reply from drviver-process
| #define ngcbTESTERR_IO_ERR3 0x103 |
test module i/o-error
| #define ngcbTESTERR_IVLD 0x104 |
test invalid address
| #define ngcbTESTERR_NO_ACK 0x100 |
test no acknowledge from HW
| #define ngcbTESTERR_SEQ_EMPTY 0x200 |
test sequencer FIFO getting empty
| #define ngcbTESTERR_SEQ_IDLE 0x201 |
test sequencer going to idle state
1.13.2