ngcdrv_pci.h

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#ifndef NGCDRV_PCI_H
#define NGCDRV_PCI_H
 
/*
 * Kernel and system headers
 */
#include <linux/module.h>
#include <linux/init.h>
#include <linux/version.h>
/* 
#include <linux/config.h> 
*/
 
#if defined(CONFIG_SMP) && !defined(__SMP__)
#define __SMP__
#endif
 
#ifdef CONFIG_DEVFS_FS
/* 
 * Uncomment the following to have the automatic /dev file system supported  
 */
/* #define NGCDRV_DEVFS */  
#endif
 
#include <linux/kernel.h>
#include <linux/compat.h>
#include <linux/errno.h>
#include <linux/types.h>
#include <linux/major.h>
#include <linux/vmalloc.h>
#include <linux/fs.h>
#ifdef NGCDRV_DEVFS
#include <linux/devfs_fs_kernel.h>
#endif
#ifdef CONFIG_PROC_FS
#include <linux/proc_fs.h>
#if LINUX_VERSION_CODE < KERNEL_VERSION(3,10,0)
#define NGCDRV_PROC_FS_v1
#else
#include <linux/seq_file.h>
#define NGCDRV_PROC_FS_v2
#endif
#endif
#include <linux/mm.h>
#include <linux/sched.h>
#if LINUX_VERSION_CODE >= KERNEL_VERSION(4, 11, 0)
#include <linux/sched/signal.h>
#endif
#include <linux/interrupt.h>
#include <linux/pci.h>
#include <linux/poll.h> 
#include <linux/delay.h>
#include <linux/ioport.h>   /* for request_region */
#include <asm/io.h>     /* for ioremap */
#include <asm/uaccess.h>    /* for copy_to/from_user */
#include <asm/atomic.h>         /* for sync-counter */
 
/*
 * Local headers
 */
#include "ngcdrv_tcb.h"
#include "ngcdrv.h"

#ifdef CONFIG_X86_64
#define NGCDRV_GFP GFP_KERNEL|GFP_DMA32
#else
#define NGCDRV_GFP GFP_KERNEL
#endif

#define NGCDRV_MINOR2INST(minor) (minor >> 4)

#define NGCDRV_MINOR2SUBDEV(minor) (minor & 0x0f)

#define NGCDRV_MINOR(instance,i)  ((instance << 4) | (i))

enum ngcdrv_minors {
  COM_MINOR = 0,
  COMX1_MINOR,
  COMX2_MINOR,
  COMX3_MINOR,
  DMA_MINOR
};
 
/*
 * Vendor-id and device-id - this is used to assign the 
 * device driver to our physical device
 */
#define NGCDRV_PCI_VENDOR_ID 0x10ee   
#define NGCDRV_PCI_DEVICE_ID 0x5043   
 
/* 
 * Supported board types (subsystem-id)
 */
#define NGCDRV_BTYPE_XILINX_PCI  0x1111   
#define NGCDRV_BTYPE_XILINX_PCIE 0x0007   
 
/*
 * Latency
 */
/*#define NGCDRV_PCI_LATENCY (SMP_CACHE_BYTES >> 2) */
/*#define NGCDRV_PCI_LATENCY 248 */
 
/* 
 * Macros for done-count wrap around
 */
#define NGCDRV_WRAP_CNT 0xffffffff
#define NGCDRV_INC(x) if(*x==NGCDRV_WRAP_CNT) {*x=0;} else {(*x)++;}
#define NGCDRV_DEC(x) if(*x==0) {*x=NGCDRV_WRAP_CNT;} else {(*x)--;}
#define NGCDRV_DIFF(x,a,b) if(b<a){*x=(NGCDRV_WRAP_CNT-a)+b;}else{*x=b-a;}

#define NGCDRV_CFG_REG_SIZE 256

#define NGCDRV_NUM_CHAN 4
 
/* 
 * Communication port registers
 */
#define NGCDRV_REG_CTRL       0x1C       
#define NGCDRV_REG_CTRL_X1    0x2C       
#define NGCDRV_REG_CTRL_X2    0x3C       
#define NGCDRV_REG_CTRL_X3    0x4C       
#define NGCDRV_REG_STAT       0x14       
#define NGCDRV_REG_STAT_X1    0x24       
#define NGCDRV_REG_STAT_X2    0x34       
#define NGCDRV_REG_STAT_X3    0x44       
#define NGCDRV_REG_FIFO       0x10       
#define NGCDRV_REG_FIFO_X1    0x20       
#define NGCDRV_REG_FIFO_X2    0x30       
#define NGCDRV_REG_FIFO_X3    0x40       
#define NGCDRV_CTRL_CLRCOM    0x00000001  
#define NGCDRV_CTRL_CLRDMA    0x00000002  
#define NGCDRV_CTRL_TRANSFER  0x00000010  
#define NGCDRV_CTRL_RESET     0x00008000 
 
/* 
 * DMA registers 
 */
#define NGCDRV_DMA_REG_DESCR  0x90     
#define NGCDRV_DMA_REG_CMD    0xA8     
#define NGCDRV_DMA_REG_IRQ    0x68     
#define NGCDRV_DMA_REG_LCNT   0xA4     
#define NGCDRV_DMA_REG_CHAN   0xC4     
 
/* 
 * Descriptor pointer register bits
 */
#define NGCDRV_DMA_DESCR_EOC  0x2      
#define NGCDRV_DMA_DESCR_INTR 0x4      
  
 
/* 
 * DMA command register bits
 */
#define NGCDRV_DMA_CMD_START     0x0002  
#define NGCDRV_DMA_CMD_ABORT     0x0004  
#define NGCDRV_DMA_CMD_INTR_CLR  0x0008  
#define NGCDRV_DMA_CMD_LCNT_MODE 0x0100  
#define NGCDRV_DMA_CMD_LCNT_STOP 0x0200  
#define NGCDRV_DMA_CMD_LCNT_CLR  0x0400  
 
/* 
 * DMA interrupt register bits
 */
#define NGCDRV_DMA_IRQ (1<<21) 
 
/*
 * DMA FIFO
 */
#define NGCDRV_DMA_REG_FIFO   NGCDRV_REG_CTRL     
#define NGCDRV_DMA_FIFO_CLR   NGCDRV_CTRL_CLRDMA  

#define NGCDRV_DMA_MAX PAGE_SIZE
 
/* 
 * DMA address space 
 */
#define NGCDRV_DMA_KERNEL 0       
#define NGCDRV_DMA_USER   1       

#define NGCDRV_USE_VAR(x) do {(void)(x);} while (0)

typedef struct 
{
    unsigned int pid;     
#ifdef CONFIG_DEVFS_FS    
    devfs_handle_t devfs; 
#endif
} ngcdrv_state_t;

typedef struct {
  uint32_t addr;       
  uint32_t addr_high;  
  uint32_t count;      
  uint32_t descptr;    
} ngcdrv_descr_t;
 
/*
 * Configuration register type
 */
typedef uint8_t ngcdrv_reg_t;

typedef struct
{
  struct work_struct work;       
  unsigned long data;            
} ngcdrv_work_t;

typedef struct 
{
  uint32_t mode;                   
  uint32_t mode_req;               
  struct tasklet_struct tasklet;   
  struct workqueue_struct *wq;     
  ngcdrv_work_t work;              
  int init;                        
  int enabled;                     
  void **dma_buffer;               
  uint32_t dma_buffer_num;         
  uint32_t dma_buffer_size;        
  uint32_t dma_rn;                 
  unsigned long dma_rsize;         
  volatile uint32_t done_count;    
  volatile uint32_t dma_count;     
  volatile uint32_t idx_in;        
  volatile uint32_t idx_out;       
  volatile uint32_t scnt;          
  uint32_t snum;                   
  void *mem;                       
  ngcdrv_tcb_t *task;              
  int taskId;                      
  int32_t param[NGCDRV_MAX_PARAM]; 
  ngcdrv_tcb_t *task_reg[NGCDRV_MAX_TCB]; 
  int realloc;                     
} ngcdrv_ipp_t;

typedef struct 
{
  ngcdrv_state_t state;      
  uint32_t tmo;              
  uint32_t rstLink;          
  uint32_t routeThrough;     
  uint32_t *fifoBuf;         
  volatile ngcdrv_reg_t *regCtrl; 
  volatile ngcdrv_reg_t *regStat; 
  volatile ngcdrv_reg_t *regFifo; 
} ngcdrv_com_t;

typedef struct 
{
  ngcdrv_state_t state;
  volatile uint32_t done_count;      
  uint32_t sg_len;                   
  spinlock_t lock;               
  volatile uint32_t overflow;        
  int aborted;                       
  int dma_inprogress;          
  int sustained;            
  int valid;                    
  void **km_buffer;                  
  uint32_t km_buffer_num;            
  uint32_t km_buffer_size;           
  uint32_t km_rn;                    
  unsigned long km_rsize;            
  void **buffer;                     
  uint32_t buffer_num;               
  uint32_t buffer_size;              
  uint32_t rn;                       
  unsigned rsize;                    
  ngcdrv_descr_t **descriptors;      
  uint32_t descr_num;                
  unsigned long descr_addr;          
  struct semaphore sem_wake;         
  struct semaphore sem_buf;          
  wait_queue_head_t wait_queue;      
  ngcdrv_ipp_t ipp;                  
  uint32_t lcnt_mode;                
  atomic_t sync_cnt;                 
  uint32_t sync_mode;               
} ngcdrv_dma_t;

typedef struct
{
  struct pci_dev* pcidev;      
  int id;            
  char name[32];           
  volatile ngcdrv_reg_t *reg_base; 
  caddr_t reg_page;        
  ngcdrv_com_t COM[NGCDRV_NUM_CHAN]; 
  ngcdrv_dma_t DMA;            
  int irq;              
  int irq_realtime;        
  int irq_sharable;        
  int irq_same;            
  int irq_init;                
  unsigned long irq_count;     
  int latency;              
  int version;                 
  int btype;                   
  int dma_width;                      
  spinlock_t lock;         
 
  /*
   * These are "volatile" because interrupt handlers might change them
   * or, in the case of the registers, they talk to memory-mapped IO.
   */
  volatile const char* err_status;  
  volatile unsigned int dma_errors; 
  volatile unsigned int dma_report; 
  
} ngcdrv_t;

#ifndef SA_SHIRQ
#define NGCDRV_IRQ_SHARED IRQF_SHARED
#else
#define NGCDRV_IRQ_SHARED SA_SHIRQ
#endif
 
#endif /* !NGCDRV_PCI_H */